In the semiconductor integrated circuit (IC) industry, technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing.
One aspect of forming integrated circuits is forming small vertical metal lines to connect one layer of horizontal metal lines to a different layer of horizontal metal lines. Such vertical metal lines are typically referred to as vias. Due to the small nature of integrated circuits, aligning the pattern of vias to the previously applied layers can be difficult. For example, when fabricating vias, it is important that the pattern used to form the vias is appropriately aligned such that the vias connect to the appropriate metal lines. Even if a via makes contact with the appropriate underlying metal line, a slight misalignment may cause the via to be too close to a neighboring metal line. To avoid this issue, it is desirable to use processing methods to form vias that are better aligned and do not come too close to lines to which they are not intended to contact.